1. Field of the Invention
The present invention relates generally to manufacturing of semiconductor memory devices, and more particularly, to improvements to manufacturing of self-aligned non-volatile semiconductor memory devices.
2. Description of the Prior Art
FIG. 4 is a block diagram showing a generally known conventional non-volatile memory (hereinafter referred to as an EEPROM) in which information can be written and erased electrically.
Referring to FIG. 4, the EEPROM comprises a memory array 50 including the EEPROM cells; a row address buffer 51 externally receiving row address signals; a column address buffer 52 receiving column address signals; a row decoder 53 and a column decoder 54 decoding these address signals for applying voltage to a word line and a bit line connected to a specified memory cell; a sense amplifier 56 for reading a signal stored in the memory cell designated by two decoders through a Y gate 55; an output buffer 57 for outputting the read signal; and a control signal input buffer 58 receiving external control signals to apply the same to respective portions.
In operation, the sense amplifier 56 detects the signal stored in the memory cell, and amplifies the signal to apply the same to the output buffer 57. FIG. 5 is a schematic diagram showing an example of the memory array 50 and the Y gate 55 shown in FIG. 4.
Referring to FIG. 5, the Y gate 55 comprises a transistor 8 connected between an I/O line 10 and a bit line 6, and a transistor 9 connected between a CG line 11 and a control gate line 5. A Y gate signal Y2 is applied to the gates of the transistors 8 and 9. Transistors to which a Y gate signal Y1 is applied are connected in the similar manner.
In the memory array 50, four bits of memory cells are shown. For example, one memory cell comprises a memory transistor 3 having a floating gate, and a selecting transistor 2 having its gate connected to a word line 1 for applying a signal stored in the memory transistor 3 to a bit line 6. Another selecting transistor 4 has its gate connected to the word line 1 to apply a signal on a control gate line 5 to the gate of the memory transistor 3.
In operation, the memory transistor 3 stores a binary signal dependent on whether electrons are stored or not in the floating gate thereof. When electrons are stored, the threshold voltage of the transistor 3 becomes high. Therefore, the transistor 3 turns off in reading operation. A signal "1" is assigned to this state. When electrons are not stored, the threshold voltage of the transistor 3 becomes negative. Therefore, the transistor 3 turns on in reading operation. A signal "0" is assigned to this state.
A voltage for reading is applied from the sense amplifier to the bit line 6 through the transistor 8, and this voltage is further applied to the transistor 3 through the transistor 2. Consequently, it can be detected in the sense amplifier whether a current flows to the memory transistor 3 or not, thereby enabling reading of the signal stored in the memory transistor 3.
FIG. 6A is a plan view showing a structure of a memory cell constituting the memory array 50, and FIG. 6B is a cross sectional view taken along the line VI--VI of FIG. 6A. The structure of the memory cell will be described with reference to these figures. The memory cell of the EEPROM having such structure is disclosed in, for example, Japanese Patent Laying-Open Gazette No. 80779/1982.
The memory cell comprises the selecting transistor 2 and the memory transistor 3 formed on a main surface of a silicon semiconductor substrate 20. The selecting transistor 2 is constituted by a source region 21 and a drain region 22 formed by diffusing impurities to the main surface of the semiconductor substrate 20, and a selective gate 23 constituting a word line 1 for receiving a selecting signal. The drain region 22 is connected to an aluminum wiring 25 through a contact hole 24.
The memory transistor 3 comprises a drain region 21 (also serves as the source region for the selective transistor 2) and source regions 26a and 26b formed by diffusing impurities on the main surface of the semiconductor substrate 20, a thin tunneling oxide film 27 formed on a prescribed region of a surface of the drain region 21, a floating gate 29 formed on a surface of the tunneling oxide film 27 or on the surface of the gate oxide film 28 of the memory transistor 3 with one end thereof extending to an upper surface of the selective gate 23, and a control gate 31 formed thereon with an insulating film 30 interposed therebetween. The floating gate 29 stores charges and carries out discharge/introduction of charges to and from the drain region 21 through the tunneling oxide film 27 corresponding to the voltage applied between the control gate 31 and the drain region 21. Introduction/discharge of electric charges is carried out utilizing so-called tunneling effect through the tunneling oxide film 27. The tunneling effect is a phenomenon in which electric charges pierce a thin tunneling oxide film 27, with the charges having lower energy than energy barrier of the oxide film.
FIG. 3A is an equivalent diagram of 1 memory cell of the EEPROM, and FIG. 3B is an equivalent circuit diagram in which 4 memory cells (4 bits) are arranged in an array. The operation of the EEPROM will be described with reference to FIGS. 3A, 3B, 6A, 6B and 6C.
When electrons are to be introduced to the floating gate 29, a high voltage is applied to the selective gate 23, so that the selecting transistor 2 turns on. The bit line 25 (aluminum wiring) is set at 0V. A programming voltage is applied to the control gate 31. The source region 26 of the memory transistor 3 is set at 0V.
When electrons are to be drawn out from the floating 29, the selective gate 23 is set at a high voltage. Consequently, the selecting transistor 2 turns on. The bit line 25 is set at the programming voltage. The control gate 31 is set at 0V. The source region 26 of the memory transistor 3 is brought to the floating state. By the setting of the above described potentials, a high electric field is applied to the region where the floating gate 29 and the drain region 21 of the memory transistor 3 are overlapped with each other through the thin insulating film 42, whereby a tunneling current flows.
In data reading, the selecting transistor 2 is turned on. An appropriate potential is applied to the bit line 25. An appropriate potential is applied to the control gate 31. The source regions 26a and 26b of the memory transistor 3 is set at 0V. Whether the memory transistor 3 turns on or remains off is determined in this state, the binary state of the floating gate 29 is checked in accordance with the determination.
The process for manufacturing the conventional EEPROM memory cell will be described with reference to FIGS. 7A to 7G.
First, as shown in FIG. 7A, a first oxide film 32 is formed on the semiconductor substrate 20, a polysilicon layer is deposited and patterned to form the selective gate 23 of the selecting transistor 2.
Thereafter, as shown in FIG. 7B, a resist 33 is applied on the surface of the semiconductor substrate, and the resist 33 is exposed using a first mask 34 which is formed to have a prescribed pattern by the photolithography method.
As shown in FIG. 7C, the resist 33 is patterned. Ion implantation of impurities 35 is carried out on the surface of the semiconductor substrate with the resist 33 serving as a mask. Ion implantation is carried out with relatively small dosage of about 1.times.10.sup.14 /cm.sup.2. Consequently, the source region 21 (also serves as the drain region of the memory transistor 3) of the selecting transistor 2 and the source region 26a of the memory transistor 3 are formed on the surface of the semiconductor substrate. The source region 21 is formed to have a low concentration in order to ensure high quality of the tunneling oxide film formed thereon.
As shown in FIG. 7D, the resist 33 is again applied on the surface of the semiconductor substrate, and the resist 33 is exposed using a second mask 37 having an opening pattern for forming the tunneling oxide film.
Thereafter, as shown in. FIG. 7E, the resist 33 is developed and patterned, the first oxide film 32 deposited on the surface of the source region 21 is etched to form a thin tunneling oxide film 27.
Then, as shown in FIG. 7F, a first polysilicon layer, a second oxide film and a second polysilicon layer are deposited on the semiconductor substrate 20, and they are patterned to form the floating gate 29 the insulating film 30 and the control gate 31. Thereafter, impurity ions 35a with the dosage of 5.times.10.sup.15 /cm.sup.2 are implanted in the surface of the semiconductor substrate 20, using the control gate 31 as a mask. By the step of this ion implantation, a drain region 22 and source regions 26a and 26bhaving higher concentration than the source region 21 are formed.
As shown in FIG. 7G, an interlayer insulating film 38 is deposited on the surface where the control gate 31 is formed, and the surface of the film is made flat. A prescribed region of the interlayer insulating film 38 is opened to provide the contact hole 24, and thereafter, the aluminum wiring layer 25 is formed. The manufacturing process of the device is thus completed.
As described above, the conventional method for manufacturing EEPROMs requires two steps of photolithography. The first step is the step of forming the resist pattern for forming the source and drain regions 21, 26a and 26bof the selecting transistor 2 and of the memory transistor 3 on the semiconductor substrate 20 (FIGS. 7B and 7C). The second step is the step of forming the resist pattern for forming the tunneling oxide film 27 in the source region 21 of the selecting transistor 2 (FIGS. 7D and 7E). The photolithography step comprises a step of aligning masks in which masks for exposing the resist to a prescribed pattern are set at prescribed positions in association with the semiconductor substrate. In the step of mask alignment, there will be errors in alignment of about 0.1 .mu.m, when we consider the precision of the alignment. Therefore, the diffusion width of the diffusion region of the source region 21 of the selecting transistor 2 formed through two steps of photolithography should include the margin for the error in mask alignment. This relation will be described with reference to the figures. First, referring to FIG. 7D, the width L.sub.S of diffusion of the source region 21 should be made wider than the width of the opening width L for forming the tunneling oxide film plus the error e in mask alignment. In addition, the width L.sub.S of diffusion of the source region 21 should be wide enough to include the error e in aligning the mask 34 for forming the source and drain regions, as shown in FIG. 7B. Therefore, the width L.sub.S of diffusion of the source region 21 is formed to have the width required for the function plus the errors in mask alignment, so that unnecessary portions in the diffusion region become large. Therefore, it is a factor preventing minimization of the memory cell structure and improvement of the degree of integration.